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Q. No.The inputs \(A\) and \(B\) can be set to \(+5~\text V\) (representing logic \(1\)) or \(0~\text V\) (representing logic \(0\)). Then, the circuit in the figure below represents:
| 1. | OR - gate | 2. | AND - gate |
| 3. | NOR - gate | 4. | NAND - gate |
Subtopic: Logic gates |
70%
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By writing down the truth table or otherwise, determine the output \(X\) of the circuit given below.
| 1. | \(A\) | 2. | \(B\) |
| 3. | \(A~\text{or}~B\) | 4. | NOT \((A)\) |
Subtopic: Logic gates |
56%
From NCERT
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What will be the change in the current through the \(5~\text V\) cell if the diode \(D\) is reversed?
1. No change
2. Increases by \(0.2~\text A\)
3. Increases by \(0.3~\text A\)
4. Decreases by \(0.2~\text A \)
1. No change
2. Increases by \(0.2~\text A\)
3. Increases by \(0.3~\text A\)
4. Decreases by \(0.2~\text A \)
Subtopic: PN junction |
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Consider the circuit shown in the figure given below. The input voltage is \(V_i\), the current through the diode is \(I_z\), and the current through the load is \(I_L\).
| 1. | \(\text{If} ~{V_i}= 15~\text{V}~\text{and}~{R_L}= 40~\Omega, ~\text{and}~{I_z}= 0.375~\text{A}\) |
| 2. | \(\text{If} ~{V_i}= 10~\text{V}~\text{and}~{R_L}= 5~\Omega, ~\text{and}~{I_L}=1~\text{A}\) |
| 3. | \(\text{If} ~{V_i}= 20~\text{V}~\text{and}~{R_L}= 20~\Omega, ~\text{and}~{I_z}= 0.25~\text{A}\) |
| 4. | \(\text{If} ~{V_i}= 20~\text{V}~\text{and}~{R_L}= 10~\Omega, ~\text{and}~{I_z}= 0.5~\text{A}\) |
Subtopic: Applications of PN junction |
51%
From NCERT
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In the circuit shown in the diagram given below, \(R\) is a small resistor, \(V_i\) is the input voltage between \(A\) & \(B\) while \(V_o\) is the output voltage between \(C\) & \(D\).
Consider the following two statements and mark the correct option.
Consider the following two statements and mark the correct option.
| (I) | \(\text{If}~V_i>2~\text{V}, ~\text{then}~V_o = V_i\) |
| (II) | \(\text{If}~V_i<2~\text{V}, ~\text{then}~V_o = 2~\text{V}\) |
| 1. | (I) is True. |
| 2. | (II) is True. |
| 3. | (I) and (II) are both True. |
| 4. | (I) and (II) are both False. |
Subtopic: PN junction |
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Given below are two statements:
| Assertion (A): | The resistance of a photodiode decreases when light having photons of sufficient energy is incident on it. |
| Reason (R): | When energetic photons fall on the \(\mathrm{p\text{-}n}\) junction of a photodiode, electron-hole pairs are created due to the breaking of the valence bonds. |
| 1. | (A) is True but (R) is False. |
| 2. | (A) is False but (R) is True. |
| 3. | Both (A) and (R) are True and (R) is the correct explanation of (A). |
| 4. | Both (A) and (R) are True but (R) is not the correct explanation of (A). |
Subtopic: Applications of PN junction |
73%
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The peak voltage in the output of a half-wave rectifier is \(30 ~\text{V}.\) The RMS voltage of the output wave is: (assuming no distortion in wave)
| 1. | \(\dfrac{30}{\sqrt2}~\text{V}\) | 2. | \(15 ~\text{V}\) |
| 3. | \(\dfrac{15}{\sqrt2}~\text{V}\) | 4. | \(10 ~\text{V}\) |
Subtopic: Rectifier |
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Assume that the threshold voltage of a diode is \(0.7\) V, and the forward resistance is negligible.
The current through the circuit is:
1. \(40\) mA
2. \(54\) mA
3. \(33\) mA
4. \(26\) mA
The current through the circuit is:
1. \(40\) mA
2. \(54\) mA
3. \(33\) mA
4. \(26\) mA
Subtopic: PN junction |
58%
From NCERT
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A voltage \(V_{AB}\) is applied to the left side input and the potential differences \(V_{AX}\) and \(V_{XY}\) are measured. Assume the diodes are ideal i.e., there is no potential difference across the diodes in forward bias. Which of the following is true?
1. \(\text{If}~V_{AB}>0, V_{AX}>0\)
2. \(\text{If}~V_{AB}>0, V_{XY}>0\)
3. \(\text{If}~V_{AB}<0, V_{XY}>0\)
4. \(\text{If}~V_{AB}<0, V_{AX}>0\)
1. \(\text{If}~V_{AB}>0, V_{AX}>0\)
2. \(\text{If}~V_{AB}>0, V_{XY}>0\)
3. \(\text{If}~V_{AB}<0, V_{XY}>0\)
4. \(\text{If}~V_{AB}<0, V_{AX}>0\)
Subtopic: PN junction |
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The truth table for a circuit is given by:
Here, \(X\) represents either \(0\) or \(1\). \(A,B,\) and \(C\) are the inputs. Which of the following is the correct circuit?
| \(A\) | \(B\) | \(C\) | \(Y\) (Output) |
| \(1\) | \(X\) | \(1\) | \(1\) |
| \(0\) | \(1\) | \(X\) | \(1\) |
| All other cases | \(0\) | ||
| 1. |  |
| 2. |  |
| 3. |  |
| 4. |  |
Subtopic: Logic gates |
52%
From NCERT
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