| 1. | \(D_1\) and \(D_2\) both are forward biased |
| 2. | \(D_1\) and \(D_2\) both are reverse biased |
| 3. | Neither \(D_1\) nor \(D_2\) conducts at any time |
| 4. | \(D_1\) is reverse biased, \(D_2\) is forward biased |
| 1. | \(120\) Hz | 2. | zero |
| 3. | \(30\) Hz | 4. | \(60\) Hz |
The circuit represents a full wave bridge rectifier when switch \(S\) is open. The output voltage \((V_0)\) pattern across \(R_L\) when \(S\) is closed:
| 1. | 2. | ||
| 3. | 4. |